; even- or odd-number ed parity by uartcr1) are added to the transfer data. the transfer data formats are shown as follows. figure 11-2 transfer data format figure 11-3 caution on ch anging transfer data format note: in order to switch the transfer data format, perform transmit operations in the above figure 11-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 129 TMP86CP27AFG 11.4 transfer rate the baud rate of uart is set of uartcr1. th e example of the baud rate are shown as follows. when tc3 is used as the uart transfer rate (when uartcr1 = ?110?), the tr ansfer clock and transfer rate are determined as follows: transfer clock [hz] = tc3 source clock [hz] / ttreg3 setting value transfer rate [baud] = transfer clock [hz] / 16 11.5 data sampling method the uart receiver keeps sampling input using the cloc k selected by uartcr1 until a start bit is detected in rxd pin input. rt clock star ts detecting ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 11-4 data sampling method table 11-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
page 130 11. asynchronous serial interface (uart ) 11.6 stop bit length TMP86CP27AFG 11.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1. 11.7 parity set parity / no parity by uartcr1 and set parity type (odd- or even-numbered) by uartcr1. 11.8 transmit/receive operation 11.8.1 data transmit operation set uartcr1 to ?1?. read uartsr to check ua rtsr = ?1?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-cl ears uartsr, transfers the data to the transmit shift register and the data are sequenti ally output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if parity addition is specified. select the data transfer baud rate using uartcr1. when data transmit st arts, transmit buffer empty flag uartsr is set to ?1? a nd an inttxd interrupt is generated. while uartcr1 = ?0? and from when ?1? is written to uartcr1 to when send data are written to tdbuf, the txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transm it does not start. 11.8.2 data receive operation set uartcr1 to ?1?. when data are received vi a the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag ua rtsr is set and an intrxd interrupt is generated. select the data transfer baud rate using uartcr1. if an overrun error (oerr) occurs when data are received, the da ta are not transferre d to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting ua rtcr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 131 TMP86CP27AFG 11.9 status flag 11.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cl eared to ?0? when the rdbuf is read after read- ing the uartsr. figure 11-5 generation of parity error 11.9.2 framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is r ead after reading the uartsr. figure 11-6 generati on of framing error 11.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read af ter reading the uartsr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears ferr.
page 132 11. asynchronous serial interface (uart ) 11.9 status flag TMP86CP27AFG figure 11-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr is cleared. 11.9.4 receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 11-8 generation of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun er ror flag which should have been cleared still remains set. 11.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf, uartsr is set to ?1?, that is, when data in tdbuf are transferred to the transmit shif t register and data transmit star ts, transmit data buffer empty flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the tdbuf is written after reading the uartsr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr intrxd interrupt rdbuf after reading uartsr then rdbuf clears rbfl.
page 133 TMP86CP27AFG figure 11-9 generation of transmit data buffer empty 11.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the data transmit is stated after writing the tdbuf. figure 11-10 generation of transmit end flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd pin uartsr inttxd interrupt after reading uartsr writing tdbuf clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr uartsr inttxd interrupt data write for tdbuf
page 134 11. asynchronous serial interface (uart ) 11.9 status flag TMP86CP27AFG
page 135 TMP86CP27AFG 12. synchronous serial interface (sio) the TMP86CP27AFG has a clocked-synchronous 8-bit serial interface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. serial interface is connected to outside peripherl devices via so, si, sck port. 12.1 configuration figure 12-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so si sck siocr2 siocr1 siosr intsio interrupt request
page 136 12. synchronous serial interface (sio) 12.2 control TMP86CP27AFG 12.2 control the serial interface is controlled by sio control registers (s iocr1/siocr2). the serial interface status can be determined by reading sio status register (siosr). the transmit and receive data buffer is controlled by the siocr2. th e data buffer is assigned to address 0fa0h to 0fa7h for sio in the dbr area, and can continuously transfer up to 8 words (bytes or nibbles) at one time. when the specified number of words has been transferre d, a buffer empty (in the tran smit mode) or a buffer full (in the receive mode or tr ansmit/receive mode) interrup t (intsio) is generated. when the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock fo r each word transferred. four different wait times can be selected with siocr2. note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz] note 2: set sios to "0" and sioinh to "1" when setting the transfer mode or serial clock. note 3: siocr1 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. sio control register 1 siocr176543210 (0fa8h) sios sioinh siom sck (initial value: 0000 0000) sios indicate transfer start / stop 0: stop write only 1: start sioinh continue / abort transfer 0: continuously transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 000: 8-bit transmit mode 010: 4-bit transmit mode 100: 8-bit transmit / receive mode 101: 8-bit receive mode 110: 4-bit receive mode except the above: reserved sck serial clock select normal1/2, idle1/2 mode slow1/2 sleep1/2 mode write only dv7ck = 0 dv7ck = 1 000 fc/2 13 fs/2 5 fs/2 5 001 fc/2 8 fc/2 8 - 010 fc/2 7 fc/2 7 - 011 fc/2 6 fc/2 6 - 100 fc/2 5 fc/2 5 - 101 fc/2 4 fc/2 4 - 110 reserved 111 external clock ( input from sck pin ) sio control register 2 siocr276543210 (0fa9h) wait buf (initial value: ***0 0000)
page 137 TMP86CP27AFG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 0fa0h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: siocr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: siocr2 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. note 1: t f ; frame time, t d ; data transfer time note 2: after sios is cleared to "0", siof is cleared to "0" at the termination of transfer or the setting of sioinh to "1". figure 12-2 fr ame time (t f ) and data transfer time (t d ) note 1: do not change mulsel during sio operation. wait wait control always sets "00" except 8-bit transmit / receive mode. write only 00: t f = t d (non wait) 01: t f = 2t d (wait) 10: t f = 4t d (wait) 11: t f = 8t d (wait) buf number of transfer words (buffer address in use) 000: 1 word transfer 0fa0h 001: 2 words transfer 0fa0h ~ 0fa1h 010: 3 words transfer 0fa0h ~ 0fa2h 011: 4 words transfer 0fa0h ~ 0fa3h 100: 5 words transfer 0fa0h ~ 0fa4h 101: 6 words transfer 0fa0h ~ 0fa5h 110: 7 words transfer 0fa0h ~ 0fa6h 111: 8 words transfer 0fa0h ~ 0fa7h sio status register siosr76543210 (0fa9h) siof sef siof serial transfer operating status moni- tor 0: 1: transfer terminated transfer in process read only sef shift operating status monitor 0: 1: shift operation terminated shift operation in process multi function register mulsel76543210 (0fbbh) siosel (uart- sel) (initial value: **** **00) siosel sio function pins select 0: 1: p05 (si0), p06 (so0), p07 (sck0) p40 (si1), p41 (so1), p42 (sck1) r/w td tf (output) s ck output
page 138 12. synchronous serial interface (sio) 12.3 serial clock TMP86CP27AFG note 2: set mulsel register before performing the setting terminal of a i/o port when changing a terminal. 12.3 serial clock 12.3.1 clock source internal clock or external clock for the source clock is selected by siocr1. 12.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck pin. the sck pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 16 mhz, fs = 32.768 khz) figure 12-3 automatic wait fu nction (at 4-bit transmit mode) 12.3.1.2 external clock an external clock connected to the sck pin is used as the serial clock. in this case, output latch of this port should be set to "1". to ensure shifting, a pulse width of at least 4 machine cycles is required. this pulse is needed for the shift operatio n to execute certainly. actually, there is necessary processing time for interrupting, writing, and reading. the minimum pulse is determined by setting the mode and the pro- gram. therfore, maximum transfer frequenc y will be 488.3k bit/sec (at fc=16mhz). table 12-1 serial clock rate normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 sck clock baud rate clock baud rate clock baud rate 000 fc/2 13 1.91 kbps fs/2 5 1024 bps fs/2 5 1024 bps 001 fc/2 8 61.04 kbps fc/2 8 61.04 kbps - - 010 fc/2 7 122.07 kbps fc/2 7 122.07 kbps - - 011 fc/2 6 244.14 kbps fc/2 6 244.14 kbps - - 100 fc/2 5 488.28 kbps fc/2 5 488.28 kbps - - 101 fc/2 4 976.56 kbps fc/2 4 976.56 kbps - - 110 - - - - - - 111 external external external external external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a u t oma ti ca ll y wait function sck so
page 139 TMP86CP27AFG figure 12-4 external clock pulse width 12.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 12.3.2.1 leading edge transmitted data are shifted on the leading ed ge of the serial clock (falling edge of the sck pin input/ output). 12.3.2.2 trailing edge received data are shifted on the trailing edge of the serial clock (rising edge of the sck pin input/out- put). figure 12-5 shift edge 12.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer re gister are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 12.5 number of w ords to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by siocr2. t sckl t sckh tcyc = 4/fc (in the normal1/2, idle1/2 modes) 4/fs (in the slow1/2, sleep1/2 modes) t sckl , t sckh > 4tcyc sck pin (output) bit 1 bit 2 bit 3 * 321 3210 ** 32 *** 3 bit 0 shift register shift register bit 1 bit 0 bit 2 bit 3 0 *** **** 210 * 10 ** 3210 (a) leading edge (b) trailing edge * ; don?t care so pin si pin sck pin sck pin
page 140 12. synchronous serial interface (sio) 12.6 transfer mode TMP86CP27AFG an intsio interrupt is generated when the specified number of words has been transferred. if the number of words is to be changed during transfer , the serial interface must be stopped before making the ch ange. the number of words can be changed during automatic-wa it operation of an internal clock. in this case, the serial interface is not required to be stopped. figure 12-6 number of words to transfer (example: 1word = 4bit) 12.6 transfer mode siocr1 is used to select the tr ansmit, receive, or tr ansmit/receive mode. 12.6.1 4-bit and 8-bit transfer modes in these modes, firstly set the sio control register to the transmit mode, and then write first transmit data (number of transfer words to be transfer red) to the data buffer registers (dbr). after the data are written, the transmission is star ted by setting siocr1 to ?1?. the data are then output sequentially to the so pin in synchronous with th e serial clock, starting with the least significant bit (lsb). as soon as the lsb has been output, the data are transferred from the data buffer register to the shift register. when the final data bit has been transferred a nd the data buffer register is empty, an intsio (buffer empty) interrupt is generated to request the next transmitted data. when the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer regist er by the time the number of data words specified with the siocr2 has been transmitted . writing even one word of data can cels the automatic- wait; therefore, when transmitting two or more words, always write the ne xt word before transmission of the previous word is completed. note:automatic waits are also canceled by writing to a dbr not being used as a transmit data buffer register; there- fore, during sio do not use such dbr for other applicati ons. for example, when 3 words are transmitted, do not use the dbr of the remained 5 words. a 1 a 2 a 3 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 a 0 a 1 a 0 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (a) 1 word transmit (b) 3 words transmit (c) 3 words receive so pin intsio interrupt intsio interrupt intsio interrupt so pin si pin sck pin sck pin sck pin
page 141 TMP86CP27AFG when an external clock is used, the data must be writte n to the data buffer register before shifting next data. thus, the transfer speed is determin ed by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. the transmission is ended by clearing siocr1 to ?0? or setting siocr1 to ?1? in buffer empty interrupt service program. siocr1 is cleared, the operation will end after all bits of words are transmitted. that the transmission has ended can be determined from the status of siosr becau se siosr is cleared to ?0? when a transfer is completed. when siocr1 is set, the transmission is immediately ended and siosr is cleared to ?0?. when an external clock is used, it is also necessary to clear siocr1 to ?0? before shifting the next data; if siocr1 is not cleared before shift out, dummy data will be transmitted and the operation will end. if it is necessary to change the number of word s, siocr1 should be cleared to ?0?, then siocr2 must be rewritten after confirming that siosr has been cleared to ?0?. figure 12-7 transfer m ode (example: 8bit, 1word tr ansfer, internal clock) a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck pin (output) so pin intsio interrupt siocr1 siosr siosr siosr
page 142 12. synchronous serial interface (sio) 12.6 transfer mode TMP86CP27AFG figure 12-8 transfer mode (example: 8b it, 1word transfer , external clock) figure 12-9 transmiiied data ho ld time at end of transfer 12.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode , set siocr1 to ?1? to enable receiving. the data are then transferred to the shift register via the si pin in synchronous with the serial clock. when one word of data has been received, it is tran sferred from the shift register to the data buffer register (dbr). when the number of words specified w ith the siocr2 has been received, an intsio (buffer full) interrupt is generated to request that these data be read out. the da ta are then read from the da ta buffer registers by the interrupt service program. when the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial cloc k will stop and an automatic-wait will be initiated until the data are read. a wait will not be initiated if even one data word has been read. note:waits are also canceled by readi ng a dbr not being used as a received data buffer register is read; therefore, during sio do not use such dbr for other applications. a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck pin (input) so pin intsio interrupt siocr1 siosr siosr msb of last word t sodh = min 3.5/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 3.5/fs [s] (in the slow1/2, sleep1/2 modes) sck pin so pin siosr
page 143 TMP86CP27AFG when an external clock is used, the shift operation is synchronized with the extern al clock; therefore, the previous data are read before the next data are transferred to the data buffer register. if the previous data have not been read, the next data will not be transferred to th e data buffer register and th e receiving of any more data will be canceled. when an external clock is used, th e maximum transfer speed is determined by the delay between the time when the interrupt request is gene rated and when the data received have been read. the receiving is ended by clearing si ocr1 to ?0? or setting sio cr1 to ?1? in buffer full interrupt service program. when siocr1 is cleared, th e current data are transferred to the buffer. after siocr1 cleared, the receiving is ended at the ti me that the final bit of the data has been received. that the receiving has ended can be determined from the st atus of siosr. siosr is cleared to ?0? when the receiv- ing is ended. after confirmed the r eceiving termination, the final receiving data is read. when siocr1 is set, the receiving is immediately ended and si osr is cleared to ?0 ?. (the received data is ignored, and it is not required to be read out.) if it is necessary to change the number of words in external clock operation, siocr1 should be cleared to ?0? then siocr2 mu st be rewritten after confirming th at siosr ha s been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of data recei ving, siocr2 must be rewritten before the received data is read out. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 to ?0?, read the last data and then switch the trans- fer mode. figure 12-10 receive mode (example: 8b it, 1word transfer, internal clock) 12.6.3 8-bit trans fer / receive mode after setting the sio control register to the 8-bit transmit/recei ve mode, write the data to be transmitted first to the data buffer registers (dbr). after that, enable the transmit/receive by sett ing siocr1 to ?1?. when transmitting, the data are output from the so pin at leading edges of the serial clock. when receiving, the data are input to the si pin at th e trailing edges of the serial clock. wh en the all receive is enabled, 8-bit data are transferred from th e shift register to the data buffer regist er. an intsio interrupt is generated when the number of data words specified with the siocr2 has been tr ansferred. usually, read the receive data from the buffer register in the interrupt service. the data buffer register is used for both transmitting and receiving; therefore, always writ e the data to be transmitted af ter reading the all received data. when the internal clock is used, a wait is initiated until the received data are read and the next transfer data are written. a wait will not be initiated if ev en one transfer data word has been written. a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 dbr b a clear sios read out read out sck pin (output) si pin intsio interrupt siocr1 siosr siosr
page 144 12. synchronous serial interface (sio) 12.6 transfer mode TMP86CP27AFG when an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift oper- ation. when an external clock is us ed, the transfer speed is determined by the maximum delay between genera- tion of an interrupt request and the received data are read and the data to be transmitted next are written. the transmit/receive operatio n is ended by clearing siocr1 to ?0? or setting siocr1 to ?1? in intsio interrupt service program. when siocr1 is cleared, the current data ar e transferred to the buff er. after siocr1 cleared, the transmitting/ receiving is ended at the time that the fi nal bit of the data has been transmitted. that the transmitting/ receiving has ended can be determined from the status of siosr. siosr is cleared to ?0? when the transmitting/recei ving is ended. when siocr1 is set, the transmit/receive operation is immediately ended and siosr is cleared to ?0?. if it is necessary to change the number of words in external clock operation, siocr1 should be cleared to ?0?, then sio cr2 must be rewritten after confirmi ng that siosr has been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit/ receive operation, siocr2 must be rewritten before reading and writing of the receive/transmit data. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 to ?0?, read the last data and then switch the trans- fer mode. figure 12-11 transfer / receive mode (examp le: 8bit, 1word transfe r, internal clock) a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 c 1 c 0 c 2 c 3 c 4 c 5 c b c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clear sios dbr d a read out (c) write (a) read out (d) write (b) sck pin (output) so pin intsio interrupt siocr1 siosr siosr si pin
page 145 TMP86CP27AFG figure 12-12 transmitted data hold ti me at end of tr ansfer / receive bit 7 of last word bit 6 t sodh = min 4/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 4/fs [s] (in the slow1/2, sleep1/2 modes) sck pin so pin siosr
page 146 12. synchronous serial interface (sio) 12.6 transfer mode TMP86CP27AFG
page 147 TMP86CP27AFG 13. 10-bit ad converter (adc) the TMP86CP27AFG have a 10-bit successi ve approximation ty pe ad converter. 13.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 13-1. it consists of control register adccr1 and adccr2 , converted value register adcdr1 and adcdr2, a da converter, a sample-hold circuit, a compar ator, and a successive comparison circuit. note: before using ad converter, set appropriate value to i/o port register conbining a analog input port. for details, see the sec- tion on "i/o ports". figure 13-1 10-bit ad converter 2 4 10 8 ainds adrs r/2 r/2 r ack amd irefon ad conversion result register 1, 2 ad converter control register 1, 2 adbf eocf intadc sain n successive approximate circuit adccr2 adcdr1 adcdr2 adccr1  sample hold circuit a s en shift clock da converter analog input multiplexer y reference voltage analog comparator 2 3 control circuit vss varef avdd ain0 ain7
page 148 13. 10-bit ad converter (adc) 13.2 register configuration TMP86CP27AFG 13.2 register configuration the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels and operatio n mode (software start or repeat) in which to per- form ad conversion and controls the ad converter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time and co ntrols the connection of the da converter (ladder resistor network). 3. ad converted value register 1 (adcdr1) this register used to store the digital value fter being converted by the ad converter. 4. ad converted value register 2 (adcdr2) this register monitors the oper ating status of the ad converter. note 1: select analog input channel during ad converter stops (adcdr2 = "0"). note 2: when the analog input channel is all use dis abling, the adccr1 should be set to "1". note 3: during conversion, do not perform port output instruction to maintain a precision for all of the pins because analog inp ut port use as general input port. and for port near to anal og input, do not input intense signaling of change. note 4: the adccr1 is automatically cleared to "0" after starting conversion. note 5: do not set adccr1 newly again during ad conv ersion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop or slow/sleep mode are started, ad conver ter control register1 (adccr1) is all initialized and no data can be written in this register. therfore, to use ad converter again, set the adccr1 newly after returning to normal1 or normal2 mode. ad converter control register 1 adccr1 (000eh) 76543210 adrs amd ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: - ad conversion start r/w amd ad operating mode 00: 01: 10: 11: ad operation disable software start mode reserved repeat mode ainds analog input control 0: 1: analog input enable analog input disable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 reserved reserved reserved reserved reserved reserved reserved reserved
page 149 TMP86CP27AFG note 1: always set bit0 in adccr2 to "0" and set bit4 in adccr2 to "1". note 2: when a read instruction for adccr2, bi t6 to 7 in adccr2 read in as undefined data. note 3: after stop or slow/sleep mode are started, ad conver ter control register2 (adccr2) is all initialized and no data can be written in this register. therfore, to use ad converter again, set the adccr2 newly after returning to normal1 or normal2 mode. note 1: setting for " ? " in the above table are inhibited. fc: high frequency oscillation clock [hz] note 2: set conversion time setting should be kept more t han the following time by analog reference voltage (varef) . ad converter control register 2 adccr2 (000fh) 76543210 irefon "1" ack "0" (initial value: **0* 000*) irefon da converter (ladder resistor) connection control 0: 1: connected only during ad conversion always connected r/w ack ad conversion time select (refer to the following table about the con- version time) 000: 001: 010: 011: 100: 101: 110: 111: 39/fc reserved 78/fc 156/fc 312/fc 624/fc 1248/fc reserved table 13-1 ack setting and conversion time condition conversion time 16 mhz 8 mhz 4 mhz 2 mhz 10 mhz 5 mhz 2.5 mhz ack 000 39/fc - - - 19.5 s - - 15.6 s 001 reserved 010 78/fc - - 19.5 s 39.0 s - 15.6 s 31.2 s 011 156/fc - 19.5 s 39.0 s 78.0 s 15.6 s 31.2 s 62.4 s 100 312/fc 19.5 s39.0 s 78.0 s 156.0 s 31.2 s 62.4 s124.8 s 101 624/fc 39.0 s78.0 s 156.0 s - 62.4 s124.8 s- 110 1248/fc 78.0 s 156.0 s - - 124.8 s- - 111 reserved - varef = 4.5 to 5.5 v 15.6 s and more - varef = 2.7 to 5.5 v 31.2 s and more ad converted value register 1 adcdr1 (0021h) 76543210 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 (initial value: 0000 0000) ad converted value register 2 adcdr2 (0020h) 76543210 ad01 ad00 eocf adbf (initial value: 0000 ****)
page 150 13. 10-bit ad converter (adc) 13.2 register configuration TMP86CP27AFG note 1: the adcdr2 is cleared to "0" when reading the a dcdr1. therfore, the ad conversion result should be read to adcdr2 more first than adcdr1. note 2: the adcdr2 is set to "1" when ad conversion star ts, and cleared to "0" when ad conversion finished. it also is cleared upon entering stop mode or slow mode . note 3: if a read instruction is executed for a dcdr2, read data of bit3 to bit0 are unstable. eocf ad conversion end flag 0: 1: before or during conversion conversion completed read only adbf ad conversion busy flag 0: 1: during stop of ad conversion during ad conversion
page 151 TMP86CP27AFG 13.3 function 13.3.1 software start mode after setting adccr1 to ?01? (software start mode), set adccr1 to ?1?. ad conver- sion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. adrs is automatically cleared afte r ad conversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adrs newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signa l (intadc) is generated (e.g., interrupt handling rou- tine). figure 13-2 software start mode 13.3.2 repeat mode ad conversion of the voltage at the analog input pin specified by adccr1 is performed repeatedly. in this mode, ad conversion is started by setti ng adccr1 to ?1? after setting adccr1 to ?11? (repeat mode). after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. in repeat mode, each time one ad conversion is complete d, the next ad conversion is started. to stop ad conversion, set adccr1 to ?00? (disable mode) by writing 0s. the ad convert operation is stopped immediately. the converted valu e at this time is not stored in the ad converted value register. adcdr1 status eocf cleared by reading conversion result conversion result read adcdr2 intadc interrupt request adcdr2 adccr1 1st conversion result 2nd conversion result indeterminate ad conversion start ad conversion start a dcdr1 a dcdr2 conversion result read conversion result read conversion result read
page 152 13. 10-bit ad converter (adc) 13.3 function TMP86CP27AFG figure 13-3 repeat mode 13.3.3 regi ster setting 1. set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). ? specify amd for the ad converter control operation mode (software or repeat mode). 2. set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to figure 13-1 and ad converter control register 2. ? choose irefon for da converter control. 3. after setting up (1) and (2) above, set ad conversion start (adrs) of ad converter control register 1 (adccr1) to ?1?. if software start mode has been selected, ad conversi on starts immediately. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdr1) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdr2) is set to ?1?, upon wh ich time ad conversion interrupt intadc is gener- ated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. a dcdr1,adcdr2 eocf cleared by reading conversion result conversion result read a dcdr2 intadc interrupt request conversion operation a dccr1 indeterminate ad conversion start adccr1 ?11? ?00? 1st conversion result ad convert operation suspended. conversion result is not stored. 2nd conversion result 3rd conversion result a dcdr1 a dcdr2 2nd conversion result 3rd conversion result 1st conversion result conversion result read conversion result read conversion result read conversion result read conversion result read
page 153 TMP86CP27AFG 13.4 stop/slow modes during ad conversion when standby mode (stop or slow mode) is entered fo rcibly during ad conversi on, the ad convert operation is suspended and the ad converter is in itialized (adccr1 and adccr2 are initia lized to initial value). also, the conversion result is indeterminate. (conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode (sto p or slow mode).) when restored from standby mode (stop or slow mode), ad conversion is not automatically restarted, so it is necessa ry to restart ad conversion. note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage. example :after selecting the conversion time 19.5 s at 16 mhz and the analog input channel ain3 pin, perform ad con- version once. after checking eocf, read the converted value, store the lower 2 bits in address 0009eh nd store the upper 8 bits in address 0009fh in ram. the operation mode is software start mode. : (port setting) : ;set port register approrriately before setting ad converter registers. : : (refer to section i/o port in details) ld (adccr1) , 00100011b ; select ain3 ld (adccr2) , 11011000b ;select conversion time(312/fc) and operation mode set (adccr1) . 7 ; adrs = 1(ad conversion start) sloop : test (adcdr2) . 5 ; eocf= 1 ? jrs t, sloop ld a , (adcdr2) ; read result data ld (9eh) , a ld a , (adcdr1) ; read result data ld (9fh), a
page 154 13. 10-bit ad converter (adc) 13.5 analog input voltage and ad conversion result TMP86CP27AFG 13.5 analog input voltage and ad conversion result the analog input voltage is corresponded to the 10-bit dig ital value converted by the ad as shown in figure 13-4. figure 13-4 analog i nput voltage and ad c onversion result (typ.) 1 0 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 analog input voltage 1024 ad conversion result varef vss
page 155 TMP86CP27AFG 13.6 precautions about ad converter 13.6.1 restrictions for ad conv ersion interrupt (intadc) usage when an ad interrupt is used, it may not be proce ssed depending on program composition. for example, if an intadc interrupt request is generated while an inte rrupt with priority lower than the interrupt latch il15 (intadc) is being accepted, the int adc interrupt latch may be cleared without the intadc interrupt being processed. the completion of ad conversion can be detected by the following methods: (1) method not using the ad conversion end interrupt whether or not ad conversion is completed can be detected by monitoring the ad conversion end flag (eocf) by software. this can be done by polling eocf or monitoring eocf at regular intervals after start of ad conversion. (2) method for detecting ad conversion end while a lower-priority interrupt is being processed while an interrupt with priority lower than intadc is being processed, chec k the ad conversion end flag (eocf) and interrupt latch il15. if il15 = 0 and eocf = 1, call the ad conversion end interrupt processing routine with consideration given to push/pop operations . at this time, if an interrupt request with priority higher than intadc has been set, the ad conversion end interrupt processing routine will be executed first against the specified priority. if n ecessary, we recommend that the ad conversion end interrupt processing rou- tine be called after checking whether or not an interrupt request with priority higher than intadc has been set. 13.6.2 analog input pin voltage range make sure the analog input pins (ain0 to ain7) are used at voltages within varef to vss. if any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. 13.6.3 analog input shared pins the analog input pins (ain0 to ain7) are shared w ith input/output ports. when using any of the analog inputs to execute ad conversion, do not execute input/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input sh ared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 13.6.4 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 13-5. the higher the output impedance of the analog input source, more easily they are susceptible to no ise. therefore, make sure the out- put impedance of the signal source in your design is 5 k ? or less. toshiba also recommends attaching a capac- itor external to the chip. figure 13-5 analog i nput equivalent circuit and exam ple of input pin processing da converter aini analog comparator internal resistance permissible signal source impedance internal capacitance 5 k ? (typ) c = 22 pf (typ.) 5 k ? (max) note) i = 7 to 0
page 156 13. 10-bit ad converter (adc) 13.6 precautions about ad converter TMP86CP27AFG
page 157 TMP86CP27AFG 14. key-on wakeup (kwu) in the TMP86CP27AFG, the stop mode is released by not only p20( int5 / stop ) pin but also four (stop2 to stop5) pins. when the stop mode is released by stop2 to stop5 pins, the stop pin needs to be used. in details, refer to the following section " 14.2 control ". 14.1 configuration figure 14-1 key-on wakeup circuit 14.2 control stop2 to stop5 pins can controlled by key-on wakeup c ontrol register (stopcr). it can be configured as enable/disable in 1-bit unit. when thos e pins are used for stop mode releas e, configure corresponding i/o pins to input mode by i/o port register beforehand. 14.3 function stop mode can be entered by setting up the system control register (syscr1), and can be exited by detecting the "l" level on stop2 to stop5 pins, which are enabled by stopcr, for releasing stop mode (note1). key-on wakeup control register stopcr76543210 (0faah) stop5 stop4 stop3 stop2 (initial value: 0000 ****) stop5 stop mode released by stop5 0:disable 1:enable write only stop4 stop mode released by stop4 0:disable 1:enable write only stop3 stop mode released by stop3 0:disable 1:enable write only stop2 stop mode released by stop2 0:disable 1:enable write only stopcr int5 stop stop mode release signal (1: release) (0faah) stop2 stop3 stop4 stop5 stop2 stop3 stop4 stop5
page 158 14. key-on wakeup (kwu) 14.3 function TMP86CP27AFG also, each level of the stop2 to stop5 pins can be co nfirmed by reading correspondi ng i/o port data register, check all stop2 to stop5 pins "h" that is enabled by stopcr before the stop mode is startd (note2,3). note 1: when the stop mode released by the edge release mo de (syscr1 = ?0?), inhibit input from stop2 to stop5 pins by key-on wakeup control register (stopcr) or must be set "h" level into stop2 to stop5 pins that are available input during stop mode. note 2: when the stop pin input is high or stop2 to stop5 pins input which is enabled by stopcr is low, executing an instruction which starts stop mode wi ll not place in stop mode but instead will immediately start the release sequence (warm up). note 3: the input circuit of key-on wakeup input and port i nput is separated?aso each input voltage threshold value is diffrent. therefore, a value comes from port input before stop mode start may be diffrent from a value which is detected by key-on wakeup input (figure 14-2). note 4: stop pin doesn?t have the control register such as stop cr, so when stop mode is released by stop2 to stop5 pins, stop pin also should be used as stop mode release function. note 5: in stop mode, key-on wakeup pin which is enabled as input mode (for releasing stop mode) by key-on wakeup control register (stopcr) may genarate the penet ration current, so the said pin must be disabled ad conversion input (analog voltage input). note 6: when the stop mode is released by stop2 to stop5 pins, the level of stop pin should hold "l" level (figure 14-3). figure 14-2 key-on wakeup input and port input figure 14-3 priority of stop pin and stop2 to stop5 pins table 14-1 release level (edge) of stop mode pin name release level (edge) syscr1="1" (note2) syscr1="0" stop "h" level rising edge stop2 "l" level don?t use (note1) stop3 "l" level don?t use (note1) stop4 "l" level don?t use (note1) stop5 "l" level don?t use (note1) port input external pin key-on wakeup input stop pin a) stop release stop mode stop mode stop pin "l" b) release stop mode stop mode in case of stop2 to stop5 stop2 pin
page 159 TMP86CP27AFG 15. lcd driver the TMP86CP27AFG has a driver and control circuit to di rectly drive the li quid crystal device (lcd). the pins to be connected to lcd are as follows: 1. segment output port 40 pins (seg39 to seg0) 2. common output port4 pins (com3 to com0) in addition, c0, c1, v1, v2, v3 pin are provided for the lcd driver?s booster circuit. the devices that can be directly driven is sel ectable from lcd of the following drive methods: 1. 1/4 duty (1/3 bias) lcd max 160 segments(8 segments 20 digits) 2. 1/3 duty (1/3 bias) lcd max 120 segments(8 segments 15 digits) 3. 1/2 duty (1/2 bias) lcd max 80 segments(8 segments 10 digits) 4. static lcd max 40 segments(8 segments 5 digits) 15.1 configuration figure 15-1 lcd driver note: the lcd driver incorporates a ded icated divider circuit. therefore, the break function of a debugger (development tool) will not stop lcd driver output. com3 com0 v1 duty control fc/2 17 , fs/2 9 fc/2 13 fc/2 16 , fs/2 8 common driver dbr display data area display data select control timing control display data buffer register blanking control segment driver fc/2 15 lcdcr to 7 6 5 4 3 2 1 0 duty slf edsp vfsel constant voltage booster circuit bres fc/2 13 , fs/2 5 fc/2 9 fc/2 11 , fs/2 3 v2 v3 c0 c1 fc/2 10 , fs/2 2 seg0 seg39
page 160 15. lcd driver 15.2 control TMP86CP27AFG 15.2 control the lcd driver is controlled using the lcd control regist er (lcdcr). the lcd driver?s display is enabled using the edsp. note 1: when (booster circui t control) is set to ?0?, v dd v3 v2 v1 v ss should be satisfied. when is set to ?1?, 5.5 [v] v3 v dd should be satisfied. if these conditions are not satisfied, it not only affects t he quality of lcd display but also may damage the device due to over voltage of the port. note 2: when used as the booster circuit, bias should be composed to 1/3. therefore, do not set lcdcr to "10" or "11" when the booster circuit is enable. note 3: do not set slf to ?10? or ?11? in slow1/2 modes. note 4: do not set vfsel to ?11? slow1/2 modes. lcd driver control register lcdcr (0028h) 76543210 edsp bres vfsel duty slf (initial value: 0000 0000) edsp lcd display control 0: blanking 1: enables lcd display (blanking is released) r/w bres booster circuit control 0: disable (use divider resistance) 1: enable vfsel selection of boost frequency normal1/2, idle/1/2 mode slow1/2, sleep0/1/2 mode dv7ck = 0 dv7ck = 1 00 fc/2 13 fs/2 5 fs/2 5 01 fc/2 11 fs/2 3 fs/2 3 10 fc/2 10 fs/2 2 fs/2 2 11 fc/2 9 fc/2 9 ? duty selection of driving methods 00: 1/4 duty (1/3 bias) 01: 1/3 duty (1/3 bias) 10: 1/2 duty (1/2 bias) 11: static slf selection of lcd frame fre- quency normal1/2, idle/1/2 mode slow1/2, sleep0/1/2 mode dv7ck = 0 dv7ck = 1 00 fc/2 17 fs/2 9 fs/2 9 01 fc/2 16 fs/28 fs/2 8 10 fc/2 15 fc/2 15 ? 11 fc/2 13 fc/2 13 ?
page 161 TMP86CP27AFG 15.2.1 lcd driving methods as for lcd driving method, 4 types can be selected by lcdcr. the driving method is initialized in the initial program according to the lcd used. note 1: f f : frame frequency note 2: v lcd3 : lcd drive voltage figure 15-2 lcd drive wa veform (com-seg pins) v lcd3 1/f f 1/f f v lcd3 ? v lcd3 data "1" data "0" 0 data "1" ? v lcd3 data "0" 0 (b) 1/3 duty (1/3 bias) (a) 1/4 duty (1/3 bias) v lcd3 ? v lcd3 data "1" data "0" 1/f f 0 (d) static ? v lcd3 data "1" data "0" 1/f f v lcd3 0 (c) 1/2 duty (1/2 bias)
page 162 15. lcd driver 15.2 control TMP86CP27AFG 15.2.2 frame frequency frame frequency (f f ) is set according to driving method and base frequency as shown in the following table 15-1. the base frequency is selected by lcdcr acco rding to the frequency fc and fs of the basic clock to be used. note: fc: high-frequency clock [hz] note: fs: low-frequency clock [hz] table 15-1 setting of lcd frame frequency (a) at the single clock mode. at the dual clock mode (dv7ck = 0). slf base frequency [hz] frame frequency [hz] 1/4 duty 1/3 duty 1/2 duty static 00 (fc = 16 mhz) 122 163 244 122 (fc = 8 mhz) 61 81 122 61 01 (fc = 8 mhz) 122 163 244 122 (fc = 4 mhz) 61 81 122 61 10 (fc = 4 mhz) 122 163 244 122 (fc = 2 mhz) 61 81 122 61 11 (fc = 1 mhz) 122 163 244 122 table 15-2 (b) at the dual clock mode (dv7ck = 1 or sysck = 1) slf base frequency [hz] frame frequency [hz] 1/4 duty 1/3 duty 1/2 duty static 00 (fs = 32.768 khz) 64 85 128 64 01 (fs = 32.768 khz) 128 171 256 128 fc 2 17 -------- fc 2 17 -------- 4 3 -- - fc 2 17 -------- ? 4 2 -- - fc 2 17 -------- ? fc 2 17 -------- fc 2 16 -------- fc 2 16 -------- 4 3 -- - fc 2 16 -------- ? 4 2 -- - fc 2 16 -------- ? fc 2 16 -------- fc 2 15 -------- fc 2 15 -------- 4 3 -- - fc 2 15 -------- ? 4 2 -- - fc 2 15 -------- ? fc 2 15 -------- fc 2 13 -------- fc 2 13 -------- 4 3 -- - fc 2 13 -------- ? 4 2 -- - fc 2 13 -------- ? fc 2 13 -------- fs 2 9 ----- - fs 2 9 ----- - 4 3 -- - fs 2 9 ----- - ? 4 2 -- - fs 2 9 ----- - ? fs 2 9 ----- - fs 2 8 ----- - fs 2 8 ----- - 4 3 -- - fs 2 8 ----- - ? 4 2 -- - fs 2 8 ----- - ? fs 2 8 ----- -
page 163 TMP86CP27AFG 15.2.3 driving method for lcd driver in the TMP86CP27AFG, lcd driving voltages can be genera ted using either an intern al booster circuit or an external resistor divider. this selection is made in lcdcr. 15.2.3.1 when using the boost er circuit (lcdcr="1") when the reference voltage is conn ected to the v1 pin, the booster circuit boosts the reference voltage twofold (v2) or threefold (v3) to generate the ou tput voltages for segment/common signals. when the reference voltage is connected to the v2 pin, it is reduced to 1/2 (v1) or boosted to 3/2 (v3). when the reference voltage is connected to the v3 pin, it is reduced to 1/3 (v1) or 2/3 (v2). lcdcr is used to select the reference fr equency in the booster circuit. the faster the boost- ing frequency, the higher the segment/common drive capability, but power consumption is increased. conversely, the slower the boosting frequency, the lower the segment/common drive capability, but power consumption is reduced. if the drive capability is insufficient, the lcd may not be displayed clearly. therefore, select an optimum boosting frequency for the lcd panel to be used. table 15-3 shows the v3 pin current capacity and boosting frequency. note: when used as the booster circ uit, bias should be composed to 1/3. therefore, do not set lcdcr to "10" or "11" when t he booster circuit is enable (lcdcr="1"). v3 v2 v1 c1 c0 vdd vss keep the following condition. v 1 = v 3 reference voltage c c c c = 0.1 to 0.47 f 1/3 x v3 a) reference pin = v1 v3 v2 v1 c1 c0 vdd vss keep the following condition. v 2 = v 3 reference voltage c c c c = 0.1 to 0.47 f b) reference pin = v2 c 2/3 x v3
page 164 15. lcd driver 15.2 control TMP86CP27AFG note 1: when the TMP86CP27AFG uses the booster circuit to drive the lcd, the pow er supply and capacitor for the booster cir- cuit should be connect ed as shown above. note 2: when the reference voltage is connected to a pin other than v1, add a capacitor between v1 and gnd. note 3: the connection examples shown abov e are different from those shown in the datasheets of the existing mask or otp products. since the above connection method enhances the boosti ng characteristics, it is recommended that new boards be designed using the above connection method. (using the ex isting connection method does not affect lcd display.) figure 15-3 connection exam ples when using the booster circuit (lcdcr = ?1?) note 1: the current capacity is the amount of voltage that falls per 1 a. note 2: the boosting frequency should be selected depending on your lcd panel. note 3: for the reference pin v1 or v2, a current capacity t en times larger than the above is recommended to ensure stable oper- ation. for example, when the boosting frequency is fc/2 9 (at fc = 8 mhz), ? 1.7 mv/ a or more is recommended for the current capacity of the reference pin v1. table 15-3 v3 pin current capacity and boosting frequency (typ.) vfsel boosting frequency fc = 16 mhz fc = 8 mhz fc = 4 mhz fc = 32.768 mhz 00 fc/2 13 or fs/2 5 ? 37 mv/ a ? 80 mv/ a ? 138 mv/ a ? 76 mv/ a 01 fc/2 11 or fs/2 3 ? 19 mv/ a ? 24 mv/ a ? 37 mv/ a ? 23 mv/ a 10 fc/2 10 or fs/2 2 ? 17 mv/ a ? 19 mv/ a ? 24 mv/ a ? 18 mv/ a 11 fc/2 9 ? 16 mv/ a ? 17 mv/ a ? 19 mv/ a? v3 v2 v1 c1 c0 vdd vss keep the following condition. v 3 c c c c = 0.1 to 0.47 f c) reference pin = v3 c reference voltage v3 v2 v1 c1 c0 vdd vss keep the following condition. c c c c = 0.1 to 0.47 f d) reference pin = v3 c v 3 =
page 165 TMP86CP27AFG 15.2.3.2 when using an external resistor divider (lcdcr="0") when an external resistor divider is used, the volt age of an external power supply is divided and input on v1, v2, and v3 to generate the output voltages for segment/common signals. the smaller the external resistor value, the higher the segment/comm on drive capability, but power con- sumption is increased. conversely, the larger the external resistor value, the lower the segment/common drive capability, but power consumption is reduced. if the drive capability is insufficient, the lcd may not be displayed clearly. therefore, select an opti mum resistor value for the lcd panel to be used. figure 15-4 connection ex amples when using an exte rnal resistor divider (lcdcr = ?0?) 15.3 lcd display operation 15.3.1 display data setting display data is stored to the display data area (ass igned to address 0f80h to 0f93h, 20bytes) in the dbr. the display data which are stored in the display data ar ea is automatically read out and sent to the lcd driver by the hardware. the lcd driver generates the segment signal and common signal according to the display data and driving method. therefore, display patterns can be changed by only over writing the contents of dis- play data area by the program. table 15-5 shows the correspondence between the display data area and seg/ com pins. lcd light when display data is ?1? and turn off when ?0?. according to the driving method of lcd, the number of pixels which can be driven becomes different, and the number of bits in the display data area which is used to store display da ta also becomes different. therefore, the bits which are not used to store display data as well as the data buffer which corresponds to the addresses not connected to lcd can be used to store general user process data (see table 15-4). note:the display data memory contents become unstable when the power supply is turned on; therefore, the dis- play data memory should be initia lized by an initiation routine. adjustment of contrast adjustment of contrast adjustment of contrast r3 r2 r1 open v3 v2 c0 c1 v1 vdd vss open 1/3 bias (r1 = r2 = r3) r2 r1 open v3 v2 c0 c1 v1 vdd vss open r1 open v3 v2 c0 c1 v1 vdd vss open static keep the following conditon. v dd v 3 v 2 v 1 v ss 1/2 bias (r1 = r2)
page 166 15. lcd driver 15.3 lcd display operation TMP86CP27AFG note: ?: this bit is not used for display data 15.3.2 blanking blanking is enabled when edsp is cleared to ?0?. blanking turns off lcd through outputting a gnd level to seg/com pin. when in stop mode, edsp is cleared to ?0? and auto matically blanked. to redisplay icd after exiting stop mode, it is necessary to set edsp back to ?1?. note:during reset, the lcd segment outputs and lcd common outputs are fixed ?0? level. but the multiplex termi- nal of input/output port and lcd segment output becomes high impedance. therefore, when the reset input is long remarkably, ghost problem may appear in lcd display. table 15-4 driving method and bit for display data driving methods bit 7/3 bit 6/2 bit 5/1 bit 4/0 1/4 duty com3 com2 com1 com0 1/3 duty ? com2 com1 com0 1/2 duty ? ? com1 com0 static ? ? ? com0 table 15-5 lcd display data area (dbr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0f80h seg1 seg0 0f81h seg3 seg2 0f82h seg5 seg4 0f83h seg7 seg6 0f84h seg9 seg8 0f85h seg11 seg10 0f86h seg13 seg12 0f87h seg15 seg14 0f88h seg17 seg16 0f89h seg19 seg18 0f8ah seg21 seg20 0f8bh seg23 seg22 0f8ch seg25 seg24 0f8dh seg27 seg26 0f8eh seg29 seg28 0f8fh seg31 seg30 0f90h seg33 seg32 0f91h seg35 seg34 0f92h seg37 seg36 0f93h seg39 seg38 com3 com2 com1 com0 com3 com2 com1 com0
page 167 TMP86CP27AFG 15.4 control method of lcd driver 15.4.1 initial setting figure 15-5 shows the flowchart of initialization. figure 15-5 initial se tting of lcd driver 15.4.2 store of display data generally, display data are prepared as fixed data in program memory (rom) and stored in display data area by load command. example : to operate a 1/4 duty lcd of 40 segments 4 com-mons at fr ame frequency fc/2 16 [hz], and booster fre- quency fc/2 13 [hz] ld (lcdcr), 01000001b ; sets lcd driving method and frame frequency. boost frequency ld (p*lcr), 0ffh ; sets segment output control register. (*; port no.) : : : : ; sets the initial value of display data. ld (lcdcr), 11000001b ; display enable sets lcd driving method (duty). sets frame frequency (slf). sets segment output control registers (p*lcr (*; port no.)) initialization of display data area. display enable (edsp) (releases from blanking.) sets boost frequency (vfsel). enables booster circuit (bres)
page 168 15. lcd driver 15.4 control method of lcd driver TMP86CP27AFG note:db is a byte data difinition instruction. figure 15-6 example of com, seg pin connection (1/4 duty) example :to display using 1/4 duty lcd a numerical value wh ich corresponds to the lcd data stored in data mem- ory at address 80h (when pins com and seg are conn ected to lcd as in figure 15-6), display data become as shown in table 15-6. ld a, (80h) add a, table-$-7 ld hl, 0f80h ld w, (pc + a) ld (hl), w ret table: db 11011111b, 00000110b, 11100011b, 10100111b, 00110110b, 10110101b, 11110101b, 00010111b, 11110111b, 10110111b table 15-6 example of display data (1/4 duty) no. display display data no. display display data 0 11011111 5 101 10101 1 00000110 6 11110101 2 11100011 7 00000111 3 10100111 8 11110111 4 00110110 9 10110111 seg0 seg1 com0 com1 com2 com3
page 169 TMP86CP27AFG example 2: table 15-6 shows an example of display data which are displayed using 1/2 duty lcd in the same way as table 15-7. the connection between pins com and seg are the same as shown in figure 15-7. figure 15-7 example of com, seg pin connection note: *: don?t care table 15-7 example of display data (1/2 duty) number display data number display data high order address low order address high order address low order address 0 **01**11 **01**11 5 **11**10 **01**01 1 **00**10 **00**10 6 **11**11 **01**01 2 **10**01 **01**11 7 **01**10 **00**11 3 **10**10 **01**11 8 **11**11 **01**11 4 **11**10 **00**10 9 **11**10 **01**11 seg0 seg2 seg1 seg3 com0 com1
page 170 15. lcd driver 15.4 control method of lcd driver TMP86CP27AFG 15.4.3 example of lcd drive output figure 15-8 1/4 duty (1/3 bias) drive v lcd3 0 v lcd3 0 v lcd3 0 v lcd3 0 v lcd3 0 v lcd3 0 v lcd3 ? v lcd3 v lcd3 0 0 ? v lcd3 seg0 seg1 display data area address seg0 edsp seg1 com0 com1 com2 com3 com0-seg0 (selected) com2-seg1 (non selected) 1011 0101 com0 com1 com2 com3 0f80h
page 171 TMP86CP27AFG figure 15-9 1/3 duty (1/3 bias) drive seg2 address *: don?t care seg0 edsp seg1 seg2 com0 com1 com2 com0-seg1 (selected) com1-seg2 (non selected) seg1 seg0 com0 com1 com2 display data area *111 *010 **** *001 v lcd3 0 v lcd3 0 v lcd3 0 v lcd3 0 v lcd3 0 v lcd3 0 v lcd3 ? v lcd3 v lcd3 0 0 ? v lcd3 0f80h 0f81h
page 172 15. lcd driver 15.4 control method of lcd driver TMP86CP27AFG figure 15-10 1/2 duty (1/2 bias) drive address *: don?t care seg0 edsp seg1 seg2 com0 com1 com0-seg1 (selected) com1-seg2 (non selected) display data area **01 **01 **11 **10 v lcd3 0 vlcd3 0 vlcd3 0 vlcd3 0 vlcd3 0 vlcd3 0 vlcd3 0 ? v lcd3 seg3 vlcd3 0 com0 com2 com1 seg3 com0 com1 ? v lcd3 0f80h 0f81h
page 173 TMP86CP27AFG figure 15-11 static drive seg2 seg7 address seg5 seg4 seg3 seg0 seg1 seg6 com0 v lcd3 v lcd3 0 v lcd3 0 v lcd3 v lcd3 ? v lcd3 v lcd3 0 seg0 seg4 seg7 com0 com0-seg0 (selected) com0-seg4 (non selected) 0 ? v lcd3 edsp ***0 ***1 ***1 ***1 ***1 ***0 ***0 ***1 display data area *: don?t care 0 0 0f80h 0f81h 0f82h 0f83h
page 174 15. lcd driver 15.4 control method of lcd driver TMP86CP27AFG
page 175 TMP86CP27AFG 16. input/output circuitry 16.1 control pins the input/output circuitries of the TMP86CP27AFG control pins are shown below. note: the test pin of the tmp86ps27 does not have a pull-down resistor(r) and protect diode (d 1 ). fix the test pin at low level. control pin i/o input/ou tput circuitry remarks xin xout input output resonator connecting pins (high frequency) r f = 1.2 m ? (typ.) r o = 0.5 k ? (typ.) xtin xtout input output resonator connecting pins (low frequency) r f = 6 m ? (typ.) r o = 220 k ? (typ.) reset input hysteresis input pull-up resistor r in = 220 k ? (typ.) r = 100 ? (typ.) test input pull-down resistor r in = 70 k ? (typ.) r = 100 ? (typ.) fc r f r o osc. enable xin xout vdd vdd fs r f r o osc. enable xtin xtout vdd vdd xten r r in vdd address-trap-reset watchdog timer system-clock-reset r r in vdd r d 1
page 176 16. input/output circuitry 16.2 input/output ports TMP86CP27AFG 16.2 input/output ports port i/o input/output circuitry remarks p0 i/o tri-state output hysteresis input r = 100 ? (typ.) lcd segment output p1 i/o tri-state output r = 100 ? (typ.) lcd segment output p2 i/o sink open drain output hysteresis input r = 100 ? (typ.) p3 i/o sink open drain output or c-mos output hysteresis input high current output (n-ch) r = 100 ? (typ.) p4 i/o sink open drain output or c-mos output hysteresis input r = 100 ? (typ.) initial "high-z" seg output data output disable pin input r vdd initial "high-z" seg output data output disable pin input r vdd initial "high-z" vdd r data output pin input initial "high-z" vdd r pch control data output pin input initial "high-z" vdd r pch control data output pin input
page 177 TMP86CP27AFG note: the absolute maximum ratings of p0, p1, p5 and p7 port input voltage should be used in ? 0.3 to v dd + 0.3 volts. p5, p7 i/o sink open drain output lcd segment output r = 100 ? (typ.) p6 i/o tri-state i/o hysteresis input ain input r = 100 ? (typ.) port i/o input/output circuitry remarks initial "high-z" data output pin input seg output r initial "high-z" data output disable ain pin input vdd r
page 178 16. input/output circuitry 16.2 input/output ports TMP86CP27AFG
page 179 TMP86CP27AFG 17. electrical characteristics 17.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operat ion, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum ra ting is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or ex plode resulting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximu m rating value will ever be exceeded. (v ss = 0 v) parameter symbol pins rating unit supply voltage v dd ? 0.3 to 6.5 v input voltage v in ? 0.3 to v dd + 0.3 output voltage v out ? 0.3 to v dd + 0.3 output current (per 1 pin) i out1 p0, p1, p3, p4, p6 port ? 1.8 ma i out2 p0, p1, p2, p4, p5, p6, p7 port 3.2 i out3 p3 port 30 output current (total) i out1 p0, p1, p3, p4, p6 port ?30 i out2 p0, p1, p2, p4, p5, p6, p7 port 60 i out3 p3 port 80 power dissipation [topr = 85 c] pd 250 mw soldering temperature (time) tsld 260 (10 s) c storage temperature tstg ? 55 to 125 operating temperature topr ? 40 to 85
page 180 17. electrical characteristics 17.2 recommended operating condition TMP86CP27AFG 17.2 recommended op erating condition the recommended operating co nditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is us ed under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), malfunction may occur. thus, when designing products, which include this device, ensure that the r ecommended operating conditions for the device are always adhered to. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min max unit supply voltage v dd fc = 16 mhz normal1, 2 modes 4.5 5.5 v idle0, 1, 2 modes fc = 8 mhz normal1, 2 modes 2.7 idle0, 1, 2 modes fs = 32.768 khz slow1, 2 modes sleep0, 1, 2 modes stop mode 2.0 input high level v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 v ih3 v dd < 4.5 v v dd 0.90 input low level v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 v il3 v dd < 4.5 v v dd 0.10 clock frequency fc xin, xout v dd = 2.7 to 5.5 v 1.0 8.0 mhz v dd = 4.5 to 5.5 v 16.0 fs xtin, xtout 30.0 34.0 khz
page 181 TMP86CP27AFG 17.3 dc characteristics note 1: typical values show those at topr = 25 c, v dd = 5 v note 2: input current (i in1 , i in2 ): the current through pull-up or pull-down resistor is not included. note 3: i dd does not include i ref current. note 4: the supply currents of slow2 and sleep2 modes are equivalent to idle0, 1, 2. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input ? 0.9 ? v input current i in1 test v dd = 5.5 v, v in = 5.5 v/0 v ?? 2 a i in2 sink open drain, tri-state i in3 reset , stop input resistance r in1 test pull down ? 70 ? k ? r in2 reset pull up 100 220 450 high frequency feedback resistor rfx xin-xout ? 1.2 ? m ? low frequency feedback resistor rfxt xtin-xtout ? 6 ? output leakage current i lo1 sink open drain port v dd = 5.5 v, v out = 5.5 v ?? 2 a i lo2 tri-state port v dd = 5.5 v, v out = 5.5 v/0v ?? 2 output high voltage v oh tri-state port v dd = 4.5 v, i oh = -0.7 ma 4.1 - ? v output low voltage v ol except xout, xtout and p3 port v dd = 4.5 v, i ol = 1.6 ma - ? 0.4 output low current i ol1 except xout, xtout and p3 port v dd = 4.5 v v ol = 0.4v -1.6 ? ma i ol2 high current port (p3 port) v dd = 4.5 v, v ol = 1.0 v ? 20 ? supply current in normal1, 2 modes i dd v dd = 5.5 v v in = 5.3 v/0.2 v fc = 16 mhz fs = 32.768 khz ? 9.5 12 supply current in idle0, 1, 2 modes ? 78.5 supply current in slow1 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz ? 912 a supply current in sleep1 mode ? 711 supply current in sleep0 mode ? 59 supply current in stop mode v dd = 5.5 v v in = 5.3 v/0.2 v ? 0.5 10
page 182 17. electrical characteristics 17.4 ad conversion characteristics TMP86CP27AFG 17.4 ad conversi on characteristics note 1: the total error includes all errors except a quantiz ation error, and is defined as a maximum deviation from the ideal conversion line. note 2: conversion time is different in recommended value by power supply voltage. about conversion time, please refer to ?regist er configuration of 10-bit timer/counter?. note 3: please use input voltage to ain input pin in limit of v aref - v ss . when voltage of range outside is input, conversion val ue becomes unsettled and gives affect to other channel conversion value. note 4: analog reference voltage range: ? v aref = v aref - a vss . note 5: the a vdd pin should be fixed on the v dd level even though ad convertor is not used. (v ss = 0.0 v, 4.5 v v dd 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 1.0 ? a vdd v power supply voltage of analog control cir- cuit a vdd v dd a vss v ss analog reference voltage range ? v aref v aref - a vss 3.5 - v dd analog input voltage v ain v ss - v aref power supply current of analog reference voltage i ref v dd = a vdd = v aref = 5.5 v v ss = a vss = 0.0 v ? 0.6 1.0 ma non linearity error v dd = a vdd = 5.0 v, v ss = a vss = 0.0 v v aref = 5.0 v ? -2 lsb zero point error ? -2 full scale error ? -2 tota l e r ro r ? -4 (v ss = 0.0 v, 2.7 v v dd < 4.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd ? 1.0 ? a vdd v power supply voltage of analog control cir- cuit a vdd v dd a vss v ss analog reference voltage range dv aref v aref - a vss 2.5 ? v dd analog input voltage v ain v ss ? v aref power supply current of analog reference voltage i ref v dd = a vdd = v aref = 4.5 v v ss = a vss = 0.0 v ? 0.5 0.8 ma non linearity error v dd = a vdd = 2.7 v, v ss = a vss = 0.0 v v aref = 2.7 v ? -2 lsb zero point error ?? 2 full scale error ?? 2 tota l e r ro r ?? 4
page 183 TMP86CP27AFG 17.5 ac characteristics (v ss = 0 v, v dd = 4.5 to 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 modes 0.25 ? 4 s idle1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep1, 2 modes high-level clock pulse width twch for external clock operation (xin input) fc = 16 mhz ? 31.25 ? ns low-level clock pulse width twcl high-level clock pulse width twsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width twsl (vss = 0 v, vdd = 2.7 to 4.5 v, topr = -40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 modes 0.5 - 4 s idle1, 2 modes slow1, 2 modes 117.6 - 133.3 sleep1, 2 modes high-level clock pulse width twch for external clock operation (xin input) fc = 8 mhz - 62.5 - ns low-level clock pulse width twcl high-level clock pulse width twsh for external clock operation (xtin input) fs = 32.768 khz -15.26- s low-level clock pulse width twsl
page 184 17. electrical characteristics 17.6 recommended oscillating conditions TMP86CP27AFG 17.6 recommended osc illating conditions note 1: to ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will act ually be mounted. note 2: for the resonators to be used with toshiba microcont rollers, we recommend ceramic resonators manufactured by murata manufacturing co., ltd. for details, please visit the website of murata at the following url: http://www.murata.co.jp 17.7 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. xin xout c 2 c 1 xtin xtout (1) high-frequency oscillation (2) low-frequency oscillation c 2 c 1
page 185 TMP86CP27AFG 18. package dimensions p-qfp80-1420-0.80b unit: mm
page 186 18. package dimensions TMP86CP27AFG
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